CV
Song Wang
Ph.D. student at Chiba University, Japan. My research focuses on dependable computing, soft-error-tolerant sequential circuits, and reliability-aware VLSI design.
Education
Doctor of Engineering in Informatics
Chiba University, Japan
Oct. 2025–present
Master of Engineering in Applied and Cognitive Informatics
Chiba University, Japan
Oct. 2023–Sep. 2025
Research & Work Experience
Research Assistant
Informatics, Chiba University, Japan
Oct. 2025–Mar. 2026
Research Student
Information Engineering, Chiba University, Japan
Apr. 2023–Sep. 2023
Skills
Languages
- English: TOEIC 755, Jul. 2022
- Japanese: JLPT N2, Jan. 2020
Programming
C/C++ Python Verilog HDL Shell Makefile
EDA & Design Tools
Synopsys HSPICE Cadence Virtuoso Siemens Calibre AMD Vivado KiCad
Platforms
Linux
Publications
Journal Articles
- Song Wang and Kazuteru Namba, “Analysis of a Delay-Element-Based Technique for Enhancing Soft Error Tolerance at Input Nodes Around Clock Edges,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 34, no. 3, pp. 1017–1028, Mar. 2026. DOI: 10.1109/TVLSI.2025.3643939.
- Song Wang, Xiangqing Wei, Ji Wu, and Kazuteru Namba, “C-Element-Based Latch with DNU Tolerance and SET Resilience Around Clock Edges,” Nonlinear Theory and Its Applications, IEICE, to appear.
- Xiangqing Wei, Ji Wu, Song Wang, Yun-Ju Baek, and Kazuteru Namba, “Structure-Aware Tile-Level Scheduling for Irregular CNNs on PE-Array Accelerators,” Nonlinear Theory and Its Applications, IEICE, to appear.
International Conference Papers
- Song Wang, Ji Wu, Xiangqing Wei, and Kazuteru Namba, “A Delay-Elements-Centric Multi-Path Temporal Dispersion Structure for MNU-Tolerant Latch Design,” 2026 IEEE 15th International Conference on Communications, Circuits and Systems (ICCCAS), accepted.
- Ji Wu, Xiangqing Wei, Song Wang, and Kazuteru Namba, “XAI-Driven Semantic Decoupling for NPU Fault Injection,” 2026 IEEE 15th International Conference on Communications, Circuits and Systems (ICCCAS), accepted.
- Song Wang and Kazuteru Namba, “A Double-Node-Upset Self-Recoverable Latch with Soft Error Tolerance to Soft Errors Around Clock Edges,” 2026 IEEE 2nd International Conference on Consumer Technology – Pacific (ICCT-Pacific), Yoshida, Yamaguchi-shi, Japan, Mar. 2026, pp. 239–242. DOI: 10.1109/ICCT-Pacific69083.2026.11518797.
- Song Wang and Kazuteru Namba, “C-Element-Based Latch for Flip-Flops: Complete SNU and Partial DNU Tolerance and Resilience to Soft Errors Around Clock Edges,” 2025 1st International Conference on Consumer Technology – Pacific (ICCT-Pacific), Matsue, Japan, Mar. 2025. DOI: 10.1109/ICCT-Pacific63901.2025.11012884.
- Song Wang and Kazuteru Namba, “A Master-Slave Flip-Flop with Double-Node-Upset Self-Recovery and Soft Error Tolerance Around Clock Edges,” 2024 International Conference on Consumer Electronics – Taiwan (ICCE-Taiwan), Taichung, Taiwan, Jul. 2024. DOI: 10.1109/ICCE-Taiwan62264.2024.10674496.
Domestic Workshops and Technical Reports
- Song Wang and Kazuteru Namba, “A C-Element-Based Latch Design for Flip-Flops with Complete SNU and Partial DNU Tolerance and Enhanced Soft Error Resilience Around Clock Edges,” IEICE Technical Report, DC2024-113, Tokyo, Japan, Feb. 2025.
- Song Wang and Kazuteru Namba, “Critical Charge Measurements Around Falling Edge of Clock Signal for D Flip-Flops,” FTC Workshop, Hiroshima, Japan, Jan. 2024.
Professional service, memberships, author profiles, and frequently used academic links are summarized on the homepage.
Academic Activities and Presentations
Teaching Assistant, “Let’s Try Simulating Computations Performed in Image Processing FPGA,” Asia Student Workshop (ASW) on Information and Image Science, Chiba, Japan.
Song Wang, “Delay-Element-Based Soft-Error-Tolerant Latch with SET Tolerance at Input Nodes Around Clock Edges,” IEEE CAS Chiba Workshop, Chiba, Japan.
Exhibitor, Computer Systems Laboratory, Chiba University, SEMICON Japan Academia Area, Tokyo, Japan.
Song Wang and Kazuteru Namba, “A Delay-Element-Based Latch for Flip-Flops with Recovery from Double-Node Upsets and Tolerance to Soft Errors Around Clock Edges,” The 11th Soft Error Workshop: Radiation Effects in Semiconductors, Fukuoka, Japan.
Teaching Assistant, “Let’s Try Simulating Computations Performed in Image Processing FPGA,” Asia Student Workshop (ASW) on Information and Image Science, Chiba, Japan.
Exhibitor, Namba Laboratory, Chiba University, SEMICON Japan Academia Area, Tokyo, Japan.
Exhibitor, Namba Laboratory, Chiba University, “Namba Laboratory and Chips,” SEMICON Japan Academia Area, Tokyo, Japan.