Wang will present “A Delay-Elements-Centric Multi-Path Temporal Dispersion Structure for MNU-Tolerant Latch Design” at the 2026 IEEE 15th International Conference on Communications, Circuits and Systems (ICCCAS) in Gunma, Japan.

Wang’s paper “C-Element-Based Latch with DNU Tolerance and SET Resilience Around Clock Edges” was accepted for publication in Nonlinear Theory and Its Applications, IEICE.

Wang presented “A Double-Node-Upset Self-Recoverable Latch with Soft Error Tolerance to Soft Errors Around Clock Edges” at IEEE International Conference on Consumer Technology - Pacific 2026 in Yamaguchi, Japan.

Wang served as a teaching assistant for the hands-on session “Let’s Try Simulating Computations Performed in Image Processing FPGA” at Asia Student Workshop (ASW) on Information and Image Science, held at Chiba University.

Wang participated in the Synopsys ASIC Design Engineer Course at the Futako-Tamagawa Rise Office of Synopsys Japan G.K. in Tokyo, Japan.

Wang presented “Delay-Element-Based Soft-Error-Tolerant Latch with SET Tolerance at Input Nodes Around Clock Edges” at 2025 IEEE CASS Chiba Workshop in Chiba, Japan.

Wang participated in the Academia Area of SEMICON Japan at Tokyo Big Sight and presented a poster on behalf of the Computer Systems Laboratory, Chiba University.

Wang’s paper “Analysis of a Delay-Element-Based Technique for Enhancing Soft Error Tolerance at Input Nodes Around Clock Edges” was accepted for publication in IEEE Transactions on Very Large Scale Integration (VLSI) Systems.